The present invention relates to a nonvolatile ferroelectric memory and, in particular, to a structure for compensating for a capacitive coupling of a bit line at an end of a memory cell array.
A nonvolatile ferroelectric memory using a ferroelectric film as an information storage capacitor has recently been actively researched and developed as a semiconductor storage device of a low dissipation power. For example, the nonvolatile ferroelectric memory using ferroelectric memory cells is described in detail in U.S. Pat. 4,873,664 (Eaton, Jr.) and S. S. Eaton, Jr., et al. "A ferroelectric DRAM Cell for High Density NVRAMs", ISSCC Digest for Technical Papers, PP. 130, February 1988, and so on.
As an information storage capacitor for a ferroelectric memory cell, use is made of a ferroelectric film, etc., formed of barium titanate (BaTiO.sub.3), lead zirconate titanate (Pb(Zr, Ti)O.sub.3 :PZT), lanthanum doped lead titanate zirconate ((Pb, La) (Zr, Ti)O.sub.3 ; PLZT), lithium niobate (LiNbO.sub.3), (potassium lithium niobate) (K.sub.3 Li.sub.2 Nb.sub.5 O.sub.15), etc. These ferroelectric films, being supplied with a voltage, produce a polarization. And the voltage/polarization relation reveals what is called a hysteresis characteristic.
Generally, a memory cell section of a semiconductor memory comprises a memory cell array comprised of a matrix array of memory cells. A respective memory cell array has a functionally irrelevant dummy interconnect line at its outer edge portion, such as dummy lines and dummy bit lines. The dummy interconnect line is provided so as to prevent the thinning of an interconnect line at a specific site, as well as an unbalance, at a time of manufacture and, in use, a given potential, such as a power supply potential Vss, is connected to the dummy interconnect line.
Generally, the semiconductor memory uses many repeated blocks of the same pattern. For example, use is made of, for example, a row decoder, column decoder, a plurality of memory cell sections having a plurality of memory cell array as a repeated block. In the case where patterning is effected from a repeated section to a non-repeated section, there sometimes occurs a case where interconnect lines are narrowed due to the configuration of the semiconductor substrate's surface, a photo-proximity effect, etc. In particular, there occurs such a phenomenon at a cell for which a design rule is stricter. For example, only a bit line at one extreme end position is made narrower than the remaining ones. As a result, their associated bit lines differ in their capacitances and hence the bit line pair involved have its sense margin deteriorated and the same thing is also true of the word line.
In order to improve, for example, the thinning of such an interconnect line and unbalance of the pattern, the above-mentioned dummy line is provided outside the word and bit lines and the dummy word line and dummy bit line are electrically connected to a given potential, such as a power supply potential Vss.
In the ferroelectric memory, a memory cell at the end side of the memory cell array is operated in an environment different from that in which other memory cell arrays are arranged. In this case, the bit line at the end of the memory cell array is arranged adjacent to the dummy bit line on the outer side. When, with the dummy bit line fixed to Vss, "1" data is to be read out of the bit line at the end of the memory cell array, its read-out margin to "1" is decreased due to a capacitive coupling of the dummy bit line Vss to the bit line. Even if the data is correctly written in some case, there may sometimes occurs a case where the data cannot be read out.